Static MOS RAMs are commonly designed with memory cells having six transistors. A pair of cross-coupled N-channel transistors have their drains connected to a first supply voltage, i.e., ground, their gates connected to first and second nodes, respectively, and their sources connected to the second and first nodes, respectfully. First and second P-channel load transistors have their sources connected to a second supply voltage, i.e., V.sub.DD, their gates connected to the first and second nodes, respectfully, and their drains connected to the second and first nodes, respectfully. First and second N-channel coupling transistors have their drains connected to the second and first nodes, respectfully, their gates connected to a word line for receiving a write signal, and their sources connected to first and second data sense lines, respectfully.
A plurality of these cells are located in a row defined by each of a plurality of word lines and are located in a column between a plurality of data sense lines. In other words, each cell is uniquely coupled between a combination of word lines and data sense lines. A cell is written when a write signal is applied to the word line and complementary data signals are applied to the first and second data sense lines causing the cell to latch in one of two states. A cell is read when a write signal is applied to the word line and the latched state is sensed by the signal appearing on the first and second data sense lines. In a standby mode, the N-channel coupling transistors are disabled by removing the write signal and the N-channel cross-coupled transistors will remain latched.
However, this cell is subject to an inadvertant change of state in the standby mode due to charged particles, i.e., alpha particles, x-ray or other source of ionizing radiation, striking the first or second node and discharging the voltage thereupon. Previous attempts to overcome this problem have included placing a first resistor between the first node and the gates of the second N-channel transistor of the cross-coupled pair and the second P-channel load transistor, and placing a second resistor between the second node and the gates of the first N-channel transistor of the cross-coupled pair and the first P-channel load transistor. This presents a resistor-capacitor (RC) time constant that substantially prevents an inadvertant change of state, when the resistor is large, due to charged particles striking the first or second nodes by allowing the P-channel load transistors to recharge the nodes before the voltage on the gates on the transistors on the opposite side of the cell may be removed.
However, these resistors cause a substantial reduction in write time by delaying the data signal applied at the first and second nodes from appearing at the gates of the transistors on the other side of the cell.
Therefore, a memory cell is needed that is resistant to changing state due being struck by charged particles without sacrificing write time.